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Wireless Components
ASK/FSK Transmitter 868/433 MHz TDA7110 Version 1.0
Data Sheet December 2008
Preliminary
Revision History Current Version: Version 1.0 as of 10.12.2008 Previous Version: none Page (in previous Version) Page (in current Version) Subjects (major changes since last revision)
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Edition 2008 Published by Infineon Technologies AG, Am Campeon 1 - 12 85579 Neubiberg, Germany
(c) 2008 Infineon Technologies AG
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions, and prices, please contact the nearest Infineon Technologies Office in Germany or the Infineon Technologies Companies and Infineon Technologies Representatives worldwide (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies Components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/ or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TDA7110
Product Info
Product Info
General Description The TDA7110 is a single chip ASK/FSK Package transmitter for the frequency bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additionally features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation.

Features
fully integrated frequency synthesizer VCO without external components high efficiency power amplifier typically 10 dBm @ 3 V switchable frequency range 868-870/433-435 MHz ASK/FSK modulation low supply current typ. 13 mA@3V Keyless entry systems Remote control systems

voltage supply range 2.1 - 4 V power down mode low voltage sensor selectable crystal oscillator 6.78 MHz/13.56 MHz programmable divided clock output for C low external component count
Applications

Alarm systems Communication systems
Ordering Information
Type TDA7110 available on tape and reel
Ordering Code
Package PG-TSSOP-16
SP000524278
Wireless Components
Product Info
Data Sheet, December 2008
1
Product Description
Contents of this Chapter 1.1 1.2 1.3 1.4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
TDA7110
Product Description
1.1 Overview
The TDA7110 is a single chip ASK/FSK transmitter for the frequency bands 868-870 MHz and 433-435 MHz. The IC offers a high level of integration and needs only a few external components. The device contains a fully integrated PLL synthesizer and a high efficiency power amplifier to drive a loop antenna. A special circuit design and an unique power amplifier design are used to save current consumption and therefore to save battery life. Additional features like a power down mode, a low power detect, a selectable crystal oscillator frequency and a divided clock output are implemented. The IC can be used for both ASK and FSK modulation.
1.2 Applications

Keyless entry systems Remote control systems Alarm systems Communication systems
1.3 Features

fully integrated frequency synthesizer VCO without external components high efficiency power amplifier typ. 10 dBm @ 3 V switchable frequency range 868-870/433-435 MHz ASK/FSK modulation low supply current typ. 13 mA @ 3 V voltage supply range 2.1 - 4 V power down mode low voltage sensor selectable crystal oscillator 6.78 MHz/13.56 MHz programmable divided clock output for C low external component count
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1-2
Data Sheet, December 2008
TDA7110
Product Description
1.4 Package Outlines
Figure 1-1
PG-TSSOP-16
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1-3
Data Sheet, December 2008
2
Functional Description
Contents of this Chapter 2.1 2.2 2.3 2.4 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.5.1 2.4.5.2 2.4.5.3 2.4.6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Functional Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 Functional Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 PLL Synthesizer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Power Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 Low Power Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 PLL Enable Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Transmit Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 Recommended timing diagrams for ASK- and FSK-Modulation . . 2-12
TDA7110
Functional Description
2.1 Pin Configuration
PDW N
1
16
C S EL
LP D
2
15
FSE L
VS
3
14
PA O U T
LF
4
13
PA G N D
TD A 7110
GND 5 12 FSK G N D
A SK D TA
6
11
FSK O U T
FS KD TA
7
10
COSC
C LKO U T
8
9
C LKD IV
Pin_config.wmf
Figure 2-1 Table 2-1
IC Pin Configuration
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol PDWN LPD VS LF GND ASKDTA FSKDTA CLKOUT CLKDIV COSC FSKOUT FSKGND PAGND PAOUT FSEL CSEL
Function Power Down Mode Control Low Power Detect Output Voltage Supply Loop Filter Ground Amplitude Shift Keying Data Input Frequency Shift Keying Data Input Clock Driver Output Clock Divider Control Crystal Oscillator Input Frequency Shift Keying Switch Output Frequency Shift Keying Ground Power Amplifier Ground Power Amplifier Output Frequency Range Selection (433 or 868 MHz) Crystal Frequency Selection (6.78 or 13.56 MHz)
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2-2
Data Sheet, December 2008
TDA7110
Functional Description
2.2 Pin Definitions and Functions
Table 2-2
Pin No. 1
Symbol PDWN
Interface Schematic1)
Function Disable pin for the complete transmitter circuit. A logic low (PDWN < 0.7 V) turns off all transmitter functions. A logic high (PDWN > 1.5 V) gives access to all transmitter functions.
VS 40 A (ASKDTA+FSKDTA)
5 k 1 "ON" 150 k
PDWN input will be pulled up by 40 A internally by either setting FSKDTA or ASKDTA to a logic high-state.
250 k
2
LPD
VS 40 A 2 300
This pin provides an output indicating the low-voltage state of the supply voltage VS. VS < 2.15 V will set LPD to the low-state. An internal pull-up current of 40 A gives the output a high-state at supply voltages above 2.15 V.
3
VS
This pin is the positive supply of the transmitter electronics. An RF bypass capacitor should be connected directly to this pin and returned to GND (pin 5) as short as possible.
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2-3
Data Sheet, December 2008
TDA7110
Functional Description
4
LF
VS
140 pF 15 pF 35 k
Output of the charge pump and input of the VCO control voltage. The loop bandwidth of the PLL is 150 kHz when only the internal loop filter is used. The loop bandwidth may be reduced by applying an external RC network referencing to the positive supply VS (pin 3).
10 k 4
5 6
GND ASKDTA
+1.2 V
General ground connection. Digital amplitude modulation can be imparted to the Power Amplifier through this pin. A logic high (ASKDTA > 1.5 V or open) enables the Power Amplifier.
+1.1 V 90 k 50 pF 30 A
60 k 6
A logic low (ASKDTA < 0.5 V) disables the Power Amplifier.
7
FSKDTA
+1.2 V
Digital frequency modulation can be imparted to the Xtal Oscillator by this pin. The VCO-frequency varies in accordance to the frequency of the reference oscillator.
+1.1 V
60 k 7 90 k 30 A
A logic high (FSKDTA > 1.5V or open) sets the FSK switch to a high impedance state. A logic low (FSKDTA < 0.5 V) closes the FSK switch from FSKOUT (pin 11) to FSKGND (pin 12). A capacitor can be switched to the reference crystal network this way. The Xtal Oscillator frequency will be shifted giving the designed FSK frequency deviation.
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2-4
Data Sheet, December 2008
TDA7110
Functional Description
8
CLKOUT
8 300
Clock output to supply an external device. An external pull-up resistor has to be added in accordance to the driving requirements of the external device. A clock frequency of 3.39 MHz is selected by a logic low at CLKDIV input (pin 9). A clock frequency of 847.5 kHz is selected by a logic high at CLKDIV input (pin 9).
9
CLKDIV
+1.2 V
60 k 9 60 k
This pin is used to select the desired clock division rate for the CLKOUT signal. VS A logic low (CLKDIV < 0.2 V) applied to this pin selects the 3.39 MHz output signal at 5 A CLKOUT (pin 8). A logic high (CLKDIV open) applied to this pin selects the 847.5 kHz output signal at +0.8 V CLKOUT (pin 8). This pin is connected to the reference oscillator circuit. The reference oscillator is working as a negative impedance converter. It presents a negative resistance in series to an inductance at the COSC pin.
10
10
COSC
VS
6 k
100 A
11
FSKOUT
VS
This pin is connected to a switch to FSKGND (pin 12). The switch is closed when the signal at FSKDTA (pin 7) is in a logic low state.
200 A 1.5 k 11
The switch is open when the signal at FSKDTA (pin 7) is in a logic high state. FSKOUT can switch an additional capacitor to the reference crystal network to pull the crystal frequency by an amount resulting in the desired FSK frequency shift of the transmitter output frequency.
12
12
FSKGND
Ground connection for FSK modulation output FSKOUT.
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Data Sheet, December 2008
TDA7110
Functional Description
13
PAGND
Ground connection of the power amplifier. The RF ground return path of the power amplifier output PAOUT (pin 14) has to be concentrated to this pin.
14
PAOUT
14
RF output pin of the transmitter. A DC path to the positive supply VS has to be supplied by the antenna matching network.
13
15
FSEL
+1.2 V
This pin is used to select the desired transmitter frequency. A logic low (FSEL < 0.5 V) applied to this pin sets the transmitter to the 433 MHz frequency range.
+1.1 V
30 k 15 90 k 30 A
A logic high (FSEL open) applied to this pin sets the transmitter to the 868 MHz frequency range.
16
CSEL
+1.2 V VS 5 A 60 k 16 +0.8 V 60 k
This pin is used to select the desired reference frequency. A logic low (CSEL < 0.2 V) applied to this pin sets the internal frequency divider to accept a reference frequency of 6.78 MHz. A logic high (CSEL open) applied to this pin sets the internal frequency divider to accept a reference frequency of 13.56 MHz.
1) Indicated voltages and currents apply for PLL Enable Mode and Transmit Mode. In Power Down Mode, the values are zero or high-ohmic.
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Data Sheet, December 2008
Wireless Components
FSK Data Input ASK Data Input Low Power Detect Output Power Down Control Positive Supply VS
Figure 2-2
7 6 1 3 2
FSK Ground
12 OR
On
FSK Switch
11
Power Supply
Low Voltage Sensor 2.2V
2.3 Functional Block diagram
Functional Block diagram
2-7
Crystal 6.78/13.56 MHz
10
XTAL Osc PFD :128/64 VCO :1/2
Power AMP
14
Power Amplifier Output
13 :2/8 :4/16 LF
Power Amplifier Ground
Clock Output Frequency Select 0.85/3.39 MHz
9 8
Clock Output Crystal Select 6.78/13.56 MHz Loop Filter
16
4
15
Frequency Select 434/868 MHz
5
Ground
TDA7110
Functional Description
Block_diagram.wmf
Data Sheet, December 2008
TDA7110
Functional Description
2.4 Functional Blocks
2.4.1 PLL Synthesizer The Phase Locked Loop synthesizer consists of a Voltage Controlled Oscillator (VCO), an asynchronous divider chain, a phase detector, a charge pump and a loop filter. It is fully implemented on chip. The tuning circuit of the VCO consisting of spiral inductors and varactor diodes is on chip, too. Therefore no additional external components are necessary. The nominal center frequency of the VCO is 869 MHz. The oscillator signal is fed both, to the synthesizer divider chain and to the power amplifier. The overall division ratio of the asynchronous divider chain is 128 in case of a 6.78 MHz crystal or 64 in case of a 13.56 MHz crystal and can be selected via CSEL (pin 16). The phase detector is a Type IV PD with charge pump. The passive loop filter is realized on chip.
2.4.2 Crystal Oscillator The crystal oscillator operates either at 6.78 MHz or at 13.56 MHz. The reference frequency can be chosen by the signal at CSEL (pin 16).
Table 2-3
CSEL (pin 16) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.2 V Pin open
Crystal Frequency 6.78 MHz 13.56 MHz
For both quartz frequency options, 847.5 kHz or 3.39 MHz are available as output frequencies of the clock output CLKOUT (pin 8) to drive the clock input of a micro controller. The frequency at CLKOUT (pin 8) is controlled by the signal at CLKDIV (pin 9)
Table 2-4
CLKDIV (pin 9) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.2 V Pin open
CLKOUT Frequency 3.39 MHz 847.5 kHz
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2-8
Data Sheet, December 2008
TDA7110
Functional Description
To achieve FSK transmission, the oscillator frequency can be detuned by a fixed amount by switching an external capacitor via FSKOUT (pin 11). The condition of the switch is controlled by the signal at FSKDTA (pin 7).
Table 2-5
FSKDTA (pin7) Low1) Open2), High3) 1) Low: 2) Open: 3) High: Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V
FSK Switch CLOSED OPEN
2.4.3 Power Amplifier
In case of operation in the 868-870 MHz band, the power amplifier is fed directly from the voltage controlled oscillator. In case of operation in the 433-435 MHz band, the VCO frequency is divided by 2. This is controlled by FSEL (pin 15) as described in the table below.
Table 2-6
FSEL (pin 15) Low1) Open2) 1) Low: 2) Open: Voltage at pin < 0.5 V Pin open
Radiated Frequency Band 433 MHz 868 MHz
The Power Amplifier can be switched on and off by the signal at ASKDTA (pin 6).
Table 2-7
ASKDTA (pin 6) Low1) Open2), High3) 1) Low: 2) Open: 3) High: Voltage at pin < 0.5 V Pin open Voltage at pin > 1.5 V
Power Amplifier OFF ON
The Power Amplifier has an Open Collector output at PAOUT (pin 14) and requires an external pull-up coil to provide bias. The coil is part of the tuning and matching LC circuitry to get best performance with the external loop antenna. To achieve the best power amplifier efficiency, the high frequency voltage swing at PAOUT (pin 14) should be twice the supply voltage. The power amplifier has its own ground pin PAGND (pin 13) in order to reduce the amount of coupling to the other circuits.
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2-9
Data Sheet, December 2008
TDA7110
Functional Description
2.4.4 Low Power Detect
The supply voltage is sensed by a low power detector. When the supply voltage drops below 2.15 V, the output LPD (pin 2) switches to the low-state. To minimize the external component count, an internal pull-up current of 40 A gives the output a high-state at supply voltages above 2.15 V. The output LPD (pin 2) can either be connected to ASKDTA (pin 6) to switch off the PA as soon as the supply voltage drops below 2.15 V or it can be used to inform a micro-controller to stop the transmission after the current data packet.
2.4.5 Power Modes
The IC provides three power modes, the POWER DOWN MODE, the PLL ENABLE MODE and the TRANSMIT MODE.
2.4.5.1 Power Down Mode In the POWER DOWN MODE the complete chip is switched off. The current consumption is typically 0.25 nA at 3 V 25C. This current doubles every 8C. The value at +85C is typically 14 nA.
2.4.5.2 PLL Enable Mode In the PLL ENABLE MODE the PLL is switched on but the power amplifier is turned off to avoid undesired power radiation during the time the PLL needs to settle. The turn on time of the PLL is determined mainly by the turn on time of the crystal oscillator and is less than 1 msec when the specified crystal is used. The current consumption is typically 4 mA. 2.4.5.3 Transmit Mode In the TRANSMIT MODE the PLL is switched on and the power amplifier is turned on too. The current consumption of the IC is typically 13 mA when using a proper transforming network at PAOUT, see Figure 3-1.
2.4.5.4 Power mode control The bias circuitry is powered up via a voltage V > 1.5 V at the pin PDWN (pin 1). When the bias circuitry is powered up, the pins ASKDTA and FSKDTA are pulled up internally. Forcing the voltage at the pins low overrides the internally set state. Alternatively, if the voltage at ASKDTA or FSKDTA is forced high externally, the PDWN pin is pulled up internally via a current source. In this case, it is not necessary to connect the PDWN pin, it is recommended to leave it open.
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2 - 10
Data Sheet, December 2008
TDA7110
Functional Description
The principle schematic of the power mode control circuitry is shown in Figure 2-5.
PDWN ASKDTA FSKDTA
On
OR
Bias Source 120 k Bias Voltage
120 k
On
FSK 868 MHz PA IC
FSKOUT
PLL
PAOUT
Power_Mode.wmf
Figure 2-5
Power mode control circuitry
Table 3-8 provides a listing of how to get into the different power modes
Table 2-8
PDWN Low1) Open2) High3) Open High Open Open 1) Low: 2) Open: 3) High:
FSKDTA Low, Open Low Low, Open, High High Low, Open, High High Low, Open, High
ASKDTA Low, Open Low Low
MODE POWER DOWN
PLL ENABLE Low Open, High Open, High High TRANSMIT
Voltage at pin < 0.7 V (PDWN) Voltage at pin < 0.5 V (FSKDTA, ASKDTA) Pin open Voltage at pin > 1.5 V
Other combinations of the control pins PDWN, FSKDTA and ASKDTA are not recommended.
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2 - 11
Data Sheet, December 2008
TDA7110
Functional Description
2.4.6 Recommended timing diagrams for ASK- and FSK-Modulation ASK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
High
FSKDTA
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
ASK_mod.wmf
Figure 2-6
ASK Modulation
FSK Modulation using FSKDTA and ASKDTA, PDWN not connected
Modes:
Power Down
PLL Enable
Transmit
DATA High
FSKDTA
Low
to t
High
ASKDTA
Low
to t
min. 1 msec.
FSK_mod.wmf
Figure 2-7
FSK Modulation
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2 - 12
Data Sheet, December 2008
TDA7110
Functional Description
Alternative ASK Modulation, FSKDTA not connected.
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to t
DATA Open, High
ASKDTA
Low
to t
min. 1 msec.
Alt_ASK_mod.wmf
Figure 2-8
Alternative ASK Modulation
Alternative FSK Modulation
Modes:
Power Down
PLL Enable
Transmit
High
PDWN
Low
to t
Open, High
ASKDTA
Low
to t
DATA Open, High
FSKDTA
Low
to t
min. 1 msec.
Alt_FSK_mod.wmf
Figure 2-9
Alternative FSK Modulation
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Data Sheet, December 2008
TDA7110
Functional Description
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2 - 14
Data Sheet, December 2008
3
Applications
Contents of this Chapter 3.1 3.2 3.3 3.4 3.5 3.6 50 Ohm-Output Testboard: Schematic . . . . . . . . . . . . . . . . . . . . . . . . 3-2 50 Ohm-Output Testboard: Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 50 Ohm-Output Testboard: Bill of material . . . . . . . . . . . . . . . . . . . . . 3-4 Application Hints on the Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . 3-5 Design hints on the buffered clock output (CLKOUT). . . . . . . . . . . . . 3-7 Application Hints on the Power-Amplifier . . . . . . . . . . . . . . . . . . . . . . 3-8
TDA7110
Applications
3.1 50 Ohm-Output Testboard: Schematic
X2SMA C8 C2
C4 L1 VCC
L2
C7 433 (868) MHz C3 C6 Q1
16
15
14
13
12
11
6.78 (13.56) MHz
TDA7110
1 2 3 4 5 6 7 8
T1 VCC
VCC
C1
R3A R3F R4 R2 ASK FSK
10
0.85 (3.4) MHz
9
R1 X1SMA
C5
50ohm_test_v5.wmf
Figure 3-1
50-output testboard schematic
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3-2
Data Sheet, December 2008
TDA7110
Applications
3.2 50 Ohm-Output Testboard: Layout
pcboben.pdf
Figure 3-2
Top Side of TDA7110-Testboard with 50 -Output
pcbunten.pdf
Figure 3-3
Bottom Side of TDA7110-Testboard with 50 -Output
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3-3
Data Sheet, December 2008
TDA7110
Applications
3.3 50 Ohm-Output Testboard: Bill of material
Table 3-1 Bill of material Part Value 434 MHz 869 MHz ASK FSK Specification
R1 R2 R3A R3F R4 C1 C2 C3 C4 C5 C6 C7
4.7k 12k 15k 15k open 47nF 27pF 6.8pF 330pF 1nF 6.8pF 0 Jumper 12pF 68nH 27nH 13.56875 MHz, CL=20pF TDA7110 Push-button SMA-S SMA-S 5.6pF 68nH 10nH 434MHz: 10pF 868MHz: 8.2pF 434MHz: 6.8pF 868MHz: 15pF 27pF 2.7pF 100pF
0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, 5% 0805, X7R, 10% 0805, COG, 5% 0805, COG, 0.1 pF 0805, COG, 5% 0805, X7R, 10% 0805, COG, 0.1 pF 6.8pF: 0805, COG, 0.1pF 15pF: 0805, COG, 1% 0805, 0 Jumper 5.6pF: 0805, COG, 0.1pF 12pF: 0805, COG, 1% TOKO LL2012-J 27nH: TOKO LL1608-J 10nH: TOKO PTL2012-J Tokyo Denpa TSS-3B 13568.75 kHz Spec.No. 10-50205
C8 L1 L2 Q1
IC1 T1 X1 X2
replaced by a short SMA standing SMA standing
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3-4
Data Sheet, December 2008
TDA7110
Applications
3.4 Application Hints on the Crystal Oscillator
The crystal oscillator achieves a turn on time less than 1 msec when the specified crystal is used. To achieve this, a NIC oscillator type is implemented in the TDA7110. The input impedance of this oscillator is a negative resistance in series to an inductance. Therefore the load capacitance of the crystal CL (specified by the crystal supplier) is transformed to the capacitance Cv.
-R
L
f, CL Cv
TDA7110
Cv =
1 1 + 2L CL
(1)
CL: : L:
crystal load capacitance for nominal frequency angular frequency inductance of the crystal oscillator
Example for the ASK-Mode:
Referring to the application circuit, in ASK-Mode the capacitance C7 is replaced by a short to ground. Assume a crystal frequency of 13.56 MHz and a crystal load capacitance of CL = 12 pF. The inductance L at 13.5 MHz is about 4.6 H. Therefore C6 is calculated to 8.567 pF, but due to parasitic capacitors of the board C6 usually has to be smaller (e.g. 6.8 pF in the ASK evalboard)
Cv =
1 1 + 2L CL
= C6
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3-5
Data Sheet, December 2008
TDA7110
Applications
Example for the FSK-Mode: FSK modulation is achieved by switching the load capacitance of the crystal as shown below.
FSKDTA
FSKOUT
Csw -R L
COSC
f, CL Cv1
Cv2
IC
The frequency deviation of the crystal oscillator is multiplied with the divider factor N of the Phase Locked Loop to the output of the power amplifier. In case of small frequency deviations (up to +/- 1000 ppm), the two desired load capacitances can be calculated with the formula below.
CL =
CL m C 0
f 2(C 0 + CL ) ) (1 + N * f1 C1 2(C 0 + CL ) f ) 1 (1 + N * f1 C1
C L: C 0: f: : N: df:
crystal load capacitance for nominal frequency shunt capacitance of the crystal frequency = 2f: angular frequency division ratio of the PLL peak frequency deviation
Because of the inductive part of the TDA7110, these values must be corrected by Formula 1). The value of Cv can be calculated.
Cv =
1 1 + 2L CL
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Data Sheet, December 2008
TDA7110
Applications
If the FSK switch is closed, Cv_ is equal to Cv1 (C6 in the application diagram). If the FSK switch is open, Cv2 (C7 in the application diagram) can be calculated.
Cv 2 = C 7 =
Csw Cv1 - (Cv + ) (Cv1 + Csw) (Cv + ) - Cv1
Csw:
parallel capacitance of the FSK switch (3 pF incl. layout parasitics)
Remark:
These calculations are only approximations. The necessary values depend on the layout also and must be adapted for the specific application board.
The 434 MHz 50-Output testboard shows an FSK-deviation of +/- 24 kHz, typically. The 868 MHz 50-Output testboard shows an FSK-deviation of +/- 27 kHz, typically.
3.5 Design hints on the buffered clock output (CLKOUT)
The CLKOUT pin is an open collector output. An external pull up resistor (RL) should be connected between this pin and the positive supply voltage. The value of RL is depending on the clock frequency and the load capacitance CLD (PCB board plus input capacitance of the microcontroller). RL can be calculated to:
RL =
1 fCLKOUT * 8 * CLD
Table 3-2 fCLKOUT= 847 kHz fCLKOUT= 3.39 MHz
CL[pF] 5 10 20 Remark:
RL[k] 27 12 6.8
CL[pF] 5 10 20
RL[k] 6.8 3.3 1.8
To achieve a low current consumption and a low spurious radiation, the largest possible RL should be chosen.
Wireless Components
3-7
Data Sheet, December 2008
TDA7110
Applications
3.6 Application Hints on the Power-Amplifier
The power amplifier operates in a high efficient class C mode. This mode is characterized by a pulsed operation of the power amplifier transistor at a current flow angle of <<. A frequency selective network at the amplifier output passes the fundamental frequency component of the pulse spectrum of the collector current to the load. The load and its resonance transformation to the collector of the power amplifier can be generalized by the equivalent circuit of Figure 3-4. The tank circuit L//C//RL in parallel to the output impedance of the transistor should be in resonance at the operating frequency of the transmitter.
VS L C RL
Equivalent_power.pdf
Figure 3-4
Equivalent power amplifier tank circuit
The optimum load at the collector of the power amplifier for "critical" operation under idealized conditions at resonance is:
R LC =
VS 2 2 PO
A typical value of RLC for an RF output power of Po= 10 mW is:
R LC =
32 = 450 2 0.01
"Critical" operation is characterized by the RF peak voltage swing at the collector of the PA transistor to just reach the supply voltage VS. The high degree of efficiency under "critical" operating conditions can be explained by the low power losses at the transistor. During the conducting phase of the transistor, its collector voltage is very small. This way the power loss of the transistor, equal to iC*uCE , is minimized. This is particularly true for small current flow angles of <<. In practice the RF-saturation voltage of the PA transistor and other parasitics reduce the "critical" RLC.
Wireless Components
3-8
Data Sheet, December 2008
TDA7110
Applications
The output power Po is reduced by operating in an "overcritical" mode characterised by RL > RLC. The power efficiency (and the bandwidth) increase when operating at a slightly higher RL, as shown in Figure 3-5. The collector efficiency E is defined as
E=
PO VS I C
The diagram of Figure 3-5 was measured directly at the PA-output at VS = 3 V. Losses in the matching circuitry decrease the output power by about 1.5 dB. As can be seen from the diagram, 250 is the optimum impedance for operation at 3 V. For an approximation of ROPT and POUT at other supply voltages those two formulas can be used:
ROPT ~ VS
and
POUT ~ ROPT
18 16 14 12 10 8 6 4 2 0 0 100 200 RL [Ohm] 300 400 500 Pout [mW] 10*Ec
Power_E_vs_RL.pdf
Figure 3-5
Output power Po (mW) and collector efficiency E vs. load resistor RL.
The DC collector current Ic of the power amplifier and the RF output power Po vary with the load resistor RL. This is typical for overcritical operation of class C amplifiers. The collector current will show a characteristic dip at the resonance frequency for this type of "overcritical" operation. The depth of this dip will increase with higher values of RL.
Wireless Components
3-9
Data Sheet, December 2008
TDA7110
Applications
As Figure 3-6 shows, detuning beyond the bandwidth of the matching circuit results in an increase of the collector current of the power amplifier and in some loss of output power. This diagram shows the data for the circuit of the test board at the frequency of 434 MHz. The behaviour at 868 MHz is similar. The effective load resistance of this circuit is RL = 250 , which is the optimum impedance for operation at 3 V. This will lead to a dip of the collector current of approx. 10%.
16
14
TDA7110 434 MHz / 3V
12
10
8
Is [mA] Pout [dBm]
6
4
2
0 375 400 425 450 475 500
f [MHz]
pout_vs_frequ.wmf
Figure 3-6
Output power and collector current vs. frequency
C3, L2-C2 and C8 are the main matching components which are used to transform the 50 load at the SMA-RF-connector to a higher impedance at the PA-output (250 @ 3 V). L1 can be used for some finetuning of the resonant frequency but should not become too small in order to keep its losses low. The transformed impedance of 250+j0 at the PA-output-pin can be verified with a network analyzer using the following measurement procedure: 1. Calibrate your network analyzer. 2. Connect some short, low-loss 50 cable to your network analyzer with an open end on one side. Semirigid cable works best. 3. Use the Port Extension" feature of your network analyzer to shift the reference plane of your network analyzer to the open end of the cable. 4. Connect the center-conductor of the cable to the solder pad of the pin PA" of the IC. The outer conductor has to be grounded. Very short connections have to be used. Do not remove the IC or any part of the matching-components! 5. Screw a 50 dummy-load on the RF-I/O-SMA-connector 6. Be sure that your network analyzer is AC-coupled and turn on the power supply of the IC. The TDA7110 has to be in PLL-Enable-Mode. 7. Measure the S-parameter S11
Wireless Components
3 - 10
Data Sheet, December 2008
TDA7110
Applications
Plot0.pdf
Figure 3-7
Sparam_measured_200M
Above you can see the measurement of the evalboard with a span of 200 MHz. The evalboard has been optimized for 3 V. The load is about 250+j0 at the transmit frequency. A tuning-free realization requires a careful design of the components within the matching network. A simple linear CAE-tool will help to see the influence of tolerances of matching components. Suppression of spurious harmonics may require some additional filtering within the antenna matching circuit. The total spectrum of the 50 -Output testboard can be summarized as:
Table 3-3 Frequency Fundamental Fund - 13.56 MHz Fund + 13.56 MHz Output Power 434 MHz Testboard +10 dBm -75 dBc -69 dBc -45 dBc -77 dBc Output Power 868 MHz Testboard +10 dBm -61 dBc -63 dBc -54 dBc -56 dBc
2
nd
harmonic
3rd harmonic
Wireless Components
3 - 11
Data Sheet, December 2008
4
Reference
Contents of this Chapter 4.1 4.2 4.3.1 4.3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 AC/DC Characteristics at 3V, 25C . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 AC/DC Characteristics at 2.1 V ... 4.0 V, -40C ... +85C. . . . . . . . . . 4-6
TDA7110
Reference
4.1 Absolute Maximum Ratings
The AC / DC characteristic limits are not guaranteed. The maximum ratings must not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC may result.
Table 4-1 Parameter Symbol Limit Values Min Junction Temperature Storage Temperature Thermal Resistance Voltage at any pin excluding pin 14 Voltage at pin 14 Current into pin 11 ESD integrity, all pins ESD integrity, all pins excluding pin 11 and pin 14 TJ Ts RthJA Vpins Vpin14 Ipin11 VESD VESD -0.3 -0.3 -10 -1 -2.5 -40 -40 Max 150 125 230 VS + 0.3 2 * VS 10 +1 +2.5 C C K/W V V mA kV kV JEDEC Standard JESD22-A114-B JEDEC Standard JESD22-A114-B No ESD-Diode to VS Unit Remarks
Ambient Temperature under bias: TA = -40C to +85C Note: All voltages referred to ground (pins) unless stated otherwise. Pins 5, 12 and 13 are grounded.
4.2 Operating Range
Within the operating range the IC operates as described in the circuit description.
Table 4-2 Parameter Symbol Limit Values Min Supply voltage Ambient temperature VS TA 2.1 -40 Max 4.0 85 V C Unit Test Conditions
Wireless Components
4-2
Data Sheet, December 2008
TDA7110
Reference
4.3 AC/DC Characteristics
4.3.1
AC/DC Characteristics at 3V, 25C
Table 4-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min Current consumption Power-Down mode PLL-Enable mode Transmit mode IS PDWN IS PLL_EN IS TRANSM 0.25 4 13.8 100 5 16.5 nA mA mA Load tank see Figure 3-1 and 3-2 V (Pins 1, 6 and 7) < 0.2 V Limit Values Typ Max Unit Test Conditions
Power Down Mode Control (Pin 1) Stand-by mode PLL enable mode Transmit mode Input bias current PDWN V PDWN V PDWN V PDWN IPDWN 0 1.5 1.5 0.7 VS VS 30 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS
Low Power Detect Output (Pin 2) Internal pull up current Input current low voltage Loop Filter (Pin 4) VCO tuning voltage Output frequency range 868 MHz-band Output frequency range 433 MHz-band VLF fOUT, 868 fOUT, 433 VS - 1.5 854 869 VS - 0.7 884 V MHz fVCO = 867.84 MHz VFSEL = VS fOUT = fVCO VFSEL = 0 V fOUT = fVCO / 2 I LPD1 I LPD2 30 1 A mA VS = 2.3 V ... VS VS = 1.9 V ... 2.1 V
427
434.5
442
MHz
ASK Modulation Data Input (Pin 6) ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VASKDTA = VS VASKDTA = 0 V
Wireless Components
4-3
Data Sheet, December 2008
TDA7110
Reference
Table 4-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min FSK Modulation Data Input (Pin 7) FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate Clock Driver Output (Pin 8) Output current (High) Saturation Voltage (Low)1) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=3.39 MHz Setting Clock Driver output frequency fCLKOUT=847.5kHz Input bias current CLKDIV Input bias current CLKDIV VCLKDIV VCLKDIV ICLKDIV ICLKDIV -20 30 0 0.2 V V A A pin open VCLKDIV = VS VCLKDIV = 0 V ICLKOUT VSATL 5 0.56 A V VCLKOUT = VS ICLKOUT = 1 mA VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA -20 20 0 1.5 0.5 VS 30 V V A A kHz VFSKDTA = VS VFSKDTA = 0 V Limit Values Typ Max Unit Test Conditions
Crystal Oscillator Input (Pin 10) Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin Serial Resistance of the crystal Input inductance of the COSC pin FSK Switch Output (Pin 11) On resistance On capacitance Off resistance Off capacitance RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10 1.5 250 6 pF k pF VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS 3.6 4.6 3.25 4.25 CCOSCmax 5 100 5.25 100 5.6 pF H H f = 6.78 MHz f = 6.78 MHz f = 13.56 MHz f = 13.56 MHz
Wireless Components
4-4
Data Sheet, December 2008
TDA7110
Reference
Table 4-3 Supply Voltage VS = 3 V, Ambient temperature Tamb = 25C Parameter Symbol Min Power Amplifier Output (Pin 14) Output Power2) transformed to 50 Ohm POUT433 POUT868 Frequency Range Selection (Pin 15) Transmit frequency 433 MHz Transmit frequency 868 MHz Input bias current FSEL Input bias current FSEL VFSEL VFSEL IFSEL IFSEL -20 25 0 0.5 V V A A pin open VFSEL = VS VFSEL = 0 V 8 10 12 dBm fOUT = 433 MHz VFSEL = 0 V fOUT = 868 MHz VFSEL = VS Limit Values Typ Max Unit Test Conditions
8
10
12
dBm
Crystal Frequency Selection (Pin 16) Crystal frequency 6.78 MHz Crystal frequency 13.56 MHz Input bias current CSEL Input bias current CSEL VCSEL VCSEL ICSEL ICSEL -20 50 0 0.2 V V A A pin open VCSEL = VS VCSEL = 0 V
1) 2)
Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA Power amplifier in overcritical C-operation Matching circuitry as used in the 50 Ohm-Output Testboard at the specified frequency. Tolerances of the passive elements not taken into account.
Wireless Components
4-5
Data Sheet, December 2008
TDA7110
Reference
4.3.2
AC/DC Characteristics at 2.1 V ... 4.0 V, -40C ... +85C
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40C ... +85C Parameter Symbol Min Current consumption Power-Down mode PLL-Enable mode Transmit mode Load tank see Figure 3-1 and 3-2 IS PDWN IS PLL_EN IS TRANSM IS TRANSM IS TRANSM Power Down Mode Control (Pin 1) Stand-by mode PLL enable mode Transmit mode Input bias current PDWN V PDWN V PDWN V PDWN IPDWN 0 1.5 1.5 0.5 VS VS 38 V V V A VASKDTA < 0.2 V VFSKDTA < 0.2 V VASKDTA < 0.5 V VASKDTA > 1.5 V VPDWN = VS 2.8 4 10.8 13.8 15.7 4 5.5 14.5 17 19 A mA mA mA mA VS = 2.1 V VS = 3.0 V VS = 4.0 V V (Pins 1, 6 and 7) < 0.2 V Limit Values Typ Max Unit Test Conditions
Low Power Detect Output (Pin 2) Internal pull up current Input current low voltage Loop Filter (Pin 4) VCO tuning voltage Output frequency range 1) 868 MHz-band Output frequency range 433 MHz-band VLF fOUT, 868 fOUT, 433 VS - 1.8 864 432 869 434.5 VS - 0.5 874 437 V MHz MHz fVCO = 867.84 MHz VFSEL = VS fOUT = fVCO VFSEL = 0 V fOUT = fVCO / 2 I LPD1 I LPD2 30 0.5 A mA VS = 2.3 V ... VS VS = 1.9 V ... 2.1 V
ASK Modulation Data Input (Pin 6) ASK Transmit disabled ASK Transmit enabled Input bias current ASKDTA Input bias current ASKDTA ASK data rate VASKDTA VASKDTA IASKDTA IASKDTA fASKDTA -20 20 0 1.5 0.5 VS 33 V V A A kHz VASKDTA = VS VASKDTA = 0 V
Wireless Components
4-6
Data Sheet, December 2008
TDA7110
Reference
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40C ... +85C Parameter Symbol Min FSK Modulation Data Input (Pin 7) FSK Switch on FSK Switch off Input bias current FSKDTA Input bias current FSKDTA FSK data rate Clock Driver Output (Pin 8) Output current (High) Saturation Voltage (Low)2) Clock Divider Control (Pin 9) Setting Clock Driver output frequency fCLKOUT=3.39 MHz Setting Clock Driver output frequency fCLKOUT=847.5kHz Input bias current CLKDIV Input bias current CLKDIV VCLKDIV VCLKDIV ICLKDIV ICLKDIV -20 30 0 0.2 V V A A pin open VCLKDIV = VS VCLKDIV = 0 V ICLKOUT VSATL 5 0.5 A V VCLKOUT = VS ICLKOUT = 0.6 mA VFSKDTA VFSKDTA IFSKDTA IFSKDTA fFSKDTA -20 20 0 1.5 0.5 VS 35 V V A A kHz VFSKDTA = VS VFSKDTA = 0 V Limit Values Typ Max Unit Test Conditions
Crystal Oscillator Input (Pin 10) Load capacitance Serial Resistance of the crystal Input inductance of the COSC pin Serial Resistance of the crystal Input inductance of the COSC pin FSK Switch Output (Pin 11) On resistance On capacitance Off resistance Off capacitance RFSKOUT CFSKOUT RFSKOUT CFSKOUT 10 1.5 280 6 pF k pF VFSKDTA = 0 V VFSKDTA = 0 V VFSKDTA = VS VFSKDTA = VS 3.2 4.6 2.9 4.25 CCOSCmax 5 100 6 100 6.3 pF H H f = 6.78 MHz f = 6.78 MHz f = 13.56 MHz f = 13.56 MHz
Wireless Components
4-7
Data Sheet, December 2008
TDA7110
Reference
Table 4-4 Supply Voltage VS = 2.1 V ... 4.0 V, Ambient temperature Tamb = -40C ... +85C Parameter Symbol Min Power Amplifier Output (Pin 14) Output Power3) at 433 MHz transformed to 50 Ohm. VFSEL = 0 V Output Power4) at 868 MHz transformed to 50 Ohm. VFSEL = VS POUT, 433 POUT, 433 POUT, 433 POUT, 868 POUT, 868 POUT, 868 5 7 7.5 5.8 7.1 7.5 6.5 10 11.5 7.5 10.2 11 8.5 12 13.5 8.5 12.2 12.5 dBm dBm dBm dBm dBm dBm VS = 2.1 V VS = 3.0 V VS = 4.0 V VS = 2.1 V VS = 3.0 V VS = 4.0 V Limit Values Typ Max Unit Test Conditions
Frequency Range Selection (Pin 15) Transmit frequency 433 MHz Transmit frequency 868 MHz Input bias current FSEL Input bias current FSEL VFSEL VFSEL IFSEL IFSEL -20 35 0 0.5 V V A A pin open VFSEL = VS VFSEL = 0 V
Crystal Frequency Selection (Pin 16) Crystal frequency 6.78 MHz Crystal frequency 13.56 MHz Input bias current CSEL Input bias current CSEL VCSEL VCSEL ICSEL ICSEL -25 55 0 0.2 V V A A pin open VCSEL = VS VCSEL = 0 V
1) The output-frequency range can be increased by limiting the temperature and supply voltage range. Minimum fVCO - 1 MHz => Minimum Tamb + 5C Maximum fVCO + 1 MHz => Maximum Tamb - 5C Maximum fVCO + 1 MHz => Minimum VS + 25 mV, max. + 40 MHz. 2) Derating linearly to a saturation voltage of max. 140 mV at ICLKOUT = 0 mA 3) Matching circuitry as used in the 50 Ohm-Output Testboard for 434 MHz operation. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25C: 6.5 dBm +/- 1 dBm Range @ 3.0 V, +25C: 10 dBm +/- 2.0 dBm Range @ 4.0 V, +25C: 11.5 dBm +/- 2.5 dBm 4) Matching circuitry as used in the 50 Ohm-Output Testboard for 868 MHz operation. Tolerances of the passive elements not taken into account. Range @ 2.1 V, +25C: 7.5 dBm +/- 1.0 dBm Range @ 3.0 V, +25C: 10.2 dBm +/- 2.0 dBm Range @ 4.0 V, +25C: 11 dBm +/- 2.5 dBm
A smaller load impedance reduces the supply-voltage dependency. A higher load impedance reduces the temperature dependency.
Wireless Components
4-8
Data Sheet, December 2008

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